Course Title: VLSI Circuits and Design Laboratory
Type of Course: Optional, Sessional
Offered to: EEE
Pre-requisite Course(s): None
Laboratory experiments and Industry level projects based on the theory course EEE 467
The objective of this course is to master the design techniques of Very Large Scale Integrated Circuits emphasizing fundamentals as well as new paradigms that need to master in today’s industry. Hence the course covers basic as well as advanced aspects of the design of Very Large Scale Integrated (VLSI) circuit from design to verification and testing.
By the end of the course, it is expected that the students will be able to design moderately complex digital VLSI chip, verify performance of the system and optimize the system for high speed and low power.
Fundamental understanding of concepts of “Electronic Circuits I” and “Digital Circuit Design” is required for this course.
| CO No. | CO Statement | Corresponding PO(s)* | Domains and Taxonomy level(s)** | Delivery Method(s) and Activity(-ies) | Assessment Tool(s) |
|---|---|---|---|---|---|
| CO1 | Apply the physics-based mathematical models of Semiconductor device to design digital circuit to do useful operation. | PO(a) | C2, C3 | Lectures, Discussions, Lab work | Lab Report, Lab Test |
| CO2 | Synthesis Digital circuits based on specific operational requirements. | PO(b) | C4, C6 | Lectures, Discussions, Lab work | Lab Report, Lab Test |
| CO3 | Design digital system based on specific requirements and design constraints such as power, speed, size etc. | PO(c), PO(d) | C4, C6 | Lectures, Discussions | Lab Report, Lab Test |
| CO4 | Apply circuit simulation tools to verify theoretical prediction of circuit performance using very complex but realistic device model. | PO(e) | C5, C6 | Lectures, Discussion Lab work |
Lab Report, Lab Test |
| CO5 | Work as a team member in a group of 4 in a Comprehensive industry standard project in collaboration with Neural Semiconductor Ltd., a leading VLSI design company in Bangladesh | PO(i) | C3, C4, C6, A3 | Lectures, Discussion Lab work |
Project Report, Project Presentation |
| CO6 | Communicate effectively with the team member and perform the design by dividing it into a number of subsystem to be completely by each member. | PO(j) | C3, C4, C6, A3 | Lectures, Discussion Lab work |
Project Report, Project Presentation |
| CO7 | To design the system cost effectively so that the cost of the chip become competitive. | PO(k) | C3, C4, C6, A3 | Lectures, Discussion Lab work |
Project Report, Project Presentation |
Cognitive Domain Taxonomy Levels: C1 – Knowledge, C2 – Comprehension, C3 – Application, C4 – Analysis, C5 – Synthesis, C6 – Evaluation, Affective Domain Taxonomy Levels: A1: Receive; A2: Respond; A3: Value (demonstrate); A4: Organize; A5: Characterize; Psychomotor Domain Taxonomy Levels: P1: Perception; P2: Set; P3: Guided Response; P4: Mechanism; P5: Complex Overt Response; P6: Adaptation; P7: Organization
Program Outcomes (PO): PO(a) Engineering Knowledge, PO(b) Problem Analysis, PO(c) Design/development Solution, PO(d) Investigation,
PO(e) Modern tool usage, PO(f) The Engineer and Society, PO(g) Environment and sustainability, PO(h) Ethics, PO(i) Individual work and team work,
PO(j). Communication, PO(k) Project management and finance, PO(l) Life-long Learning
* For details of program outcome (PO) statements, please see the departmental website or course curriculum
K 1 |
K 2 |
K 3 |
K 4 |
K 5 |
K 6 |
K 7 |
K 8 |
CP 1 |
CP 2 |
CP 3 |
CP 4 |
CP 5 |
CP 6 |
CP 7 |
CA 1 |
CA 2 |
CA 3 |
CA 4 |
CA 5 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| √ | √ | √ | √ | √ | √ | √ | √ | √ | √ | √ | √ |
| Week | Lectures | Topic |
|---|---|---|
| 1 | 1 | Introduction of overall rules, regulations, assessment methods and project related guidelines for EEE 468 Sessional Course |
| 2 | 2 | Expt-1: ASIC Front End Design: Directed Testing of a digital sub-system using Cadence NCsim. |
| 3 | 3 | Expt-2: ASIC Front End Design: Layered Verification of a digital sub-system |
| 4 | 4 | Expt-3 : RTL design of a digital sub-system and System level validation using CADENCE IUS |
| 7 | 5 | Expt-4: RTL Logic Synthesis with Cadence Genus(TM) Synthesis Solution |
| 8 | 6 | Expt-5: Physical Design of an arithmetic logic unit in Cadence Innovus. |
| 8 | 7 | Lab Test |
| 8-12 | 8 | 32 bit RISC – V Core processor design with all six types of instructions execution capability with a Memory Wrapper and a communication protocol such as APB or I2C. The students has to design and verify the processor with physical design in Cadence environment with generalized pdk. |
| 13 | 9 | Students will give power point presentation on their project performance in front of the faculties and industry experts. |
Attendance will be recorded in every class
Report on each laboratory experiment will be evaluated
Continuous assessment will be done in the form of in-class lab performance.
A lab test will be conducted at the end of the laboratory experiments.
A Comprehensive industry standard project will be given to the student in collaboration with Neural Semiconductor Ltd., a leading VLSI design company in Bangladesh, at 6th week of the course. The progress and evaluation of the project will be jointly evaluated by faculty and industry expert. The project will take 7 Weeks to complete and at the end of the project the students have to present their outcome in front of the faculty and industry experts.
Report writing 20%
Regular Lab Performance 10%
Lab Test 20%
Project performance and presentation 40%
CMOS VLSI design - A Circuits and Systems Perspective, 4th edition by Neil H. E. Weste and David Money Harris, Publisher : Addison Wesley.
Advanced Digtial Design with the Verilog HDL, Michael D. Ciletti, Prentice Hall of India Private Limited, 2005
System Verilog for Verification 3rd Edition Chris Spear and Greg Tumbush, Springer
Static Timing Analysis for Nanometer Designs – A practical Approach R. J Bhasker and Rakesh Chadha, Springer
Computer Organization and Design RISC-V Edition by David A. Patterson and John L. Hennessy, ELSEVIER
N.B. Besides going through relevant topics of the textbook, it is strongly advised that the students follow the class Lectures and discussions regularly for a thorough understanding of the topics.
Power group