Course Title: Analog Integrated Circuits and Design
Type of Course: Optional, Theory
Offered to: EEE
Pre-requisite Course(s): None
Analog IC Design: Bipolar, MOS and BiCMOS IC technology and its impact, eggshell analogy, application areas and the future of analog IC design.
Review of transistors : Large and small signal models of MOS transistors. Basic CMOS Amplifiers with passive and active loads and cascode stages.
Fabrication : Integrated circuit fabrication techniques. Photolithography steps. Fabrication sequences of CMOS circuits.
Differential pairs: Differential vs. single-ended operations of simple amplifiers, differential and common mode voltages, common mode rejection ratio (CMRR), input common mode range (ICMR), transfer characteristics, small signal analysis, and frequency response of differential pairs.
Current source/sinks : Multiple current sources/sinks using Bipolar and FET technologies. Current mirrors: Basic, cascode and active current mirrors; influence of channel modulation, mismatched transistors and error in aspect ratios. Wilson current mirror.
Constant current or voltage references: Supply voltage and temperature independent biasing, band-gap references; constant-Gm biasing. Widlar band-gap voltage reference.
High-gain amplifiers: Design and analysis of operational amplifiers (Op Amps) using MOSFETs, hierarchy in analog integrated circuits for an Op-Amps, internal structure of IC Op-Amps, high-performance Op-Amps.
Switch capacitor circuits: Equivalent resistance of a switched capacitor, unity gain buffers, charge amplifiers and integrators. Sampling switches: Charge injection, clock feed-through, charge feed-through; quantized model and remedy of charge injection. Switched capacitor filters.
Phase Lock Loop : Design of different sub-circuit of a frequency synthesizer and design of a PLL circuit.
Noise : Origin of internally developed noises in ICs; shot, thermal, flicker, burst and avalanche noises in a device. Representation of noises in circuits, noises in single stage and differential amplifiers, noise bandwidth.
The objective of this course is to master the design techniques of Analog Integrated Circuit emphasizing fundamentals as well as new paradigms that need to master in today’s industry.
The first objective is to develop the intuition first which will tell the designer where to touch to achieve the required specification. It is accomplished by the development of a solid foundation and learn the methods of analysing circuits by inspection so that the student learn what approximations can be made in which circuits and how much error to expect in each approximation.
In depth analysis of Analog integrated circuits is developed for each circuit whenever possible and discussion on simulation techniques are also discussed.
Fundamental understanding of concepts of Electronic Circuits I is required for this course.
| CO No. | CO Statement | Corresponding PO(s)* | Domains and Taxonomy level(s)** | Delivery Method(s) and Activity(-ies) | Assessment Tool(s) |
|---|---|---|---|---|---|
| CO1 | Apply the physics-based knowledge of Semiconductor device to design circuit to process Analog signals to do useful operation. | PO(a) | C3 | Lectures, Discussions | Assignment, Class test, Final exam |
| CO2 | Analyse the operation of integrated circuits (ICs) based on the underlying physics and control theory. |
PO(b) | C4 | Lectures, Discussions | Assignment, Class test, Final exam |
| CO3 | Design solid-state integrated circuits such that specified performance characteristics are attained. | PO(c) | C5 | Lectures, Discussions | Assignment, Final exam |
| CO4 | Apply circuit simulation tools to verify theoretical prediction of circuit performance using very complex but realistic device model | PO(e) | C6 | Lectures, Discussion | Assignment, Home work |
Cognitive Domain Taxonomy Levels: C1 – Knowledge, C2 – Comprehension, C3 – Application, C4 – Analysis, C5 – Synthesis, C6 – Evaluation, Affective Domain Taxonomy Levels: A1: Receive; A2: Respond; A3: Value (demonstrate); A4: Organize; A5: Characterize; Psychomotor Domain Taxonomy Levels: P1: Perception; P2: Set; P3: Guided Response; P4: Mechanism; P5: Complex Overt Response; P6: Adaptation; P7: Organization
Program Outcomes (PO): PO(a) Engineering Knowledge, PO(b) Problem Analysis, PO(c) Design/development Solution, PO(d) Investigation,
PO(e) Modern tool usage, PO(f) The Engineer and Society, PO(g) Environment and sustainability, PO(h) Ethics, PO(i) Individual work and team work,
PO(j). Communication, PO(k) Project management and finance, PO(l) Life-long Learning
* For details of program outcome (PO) statements, please see the departmental website or course curriculum
| K1 | K2 | K3 | K4 | K5 | K6 | K7 | K8 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | A1 | A2 | A3 | A4 | A5 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Week | Lectures | Topic |
|---|---|---|
| 1-3 | 1-9 | Introduction to Analog Design. Review of Basic MOS Device Physics. CMOS technology. MOS device Modelling for circuit simulation : DC and AC parameters modelling. Photolithography and CMOS Fabrication Sequences. |
| 4-6 | 10-18 | Review of MOS amplifiers. Conflicting nature of performance parameters. Common source (CS) stage, CS stage with diode connected load, CS stage with current source and triode load, CS stage with source degeneration, Source follower, Common Gate stage. Cascode stage. |
| 7-8 | 19-25 | Differential pairs: Differential vs. single-ended operations of simple amplifiers, differential and common mode voltages, transfer characteristics and voltage gain of differential pair. common mode rejection ratio (CMRR), input common mode range (ICMR), common mode to differential conversion, Gilbert Cell. |
| 9 | 26-27 | Current sink and sources, Current Mirrors. Basic, cascode and active current mirrors; influence of channel modulation, mismatched transistors and error in aspect ratios. Wilson current mirror. |
| 10 | 28-30 | Constant current or voltage references: Supply voltage and temperature independent biasing, band-gap references; constant-Gm biasing. Widlar band-gap voltage reference. |
| 11 | 31-33 | Frequency response of amplifiers: Frequency response of Common source, source follower, common gate, cascade stage and differential pairs. |
| 12 | 34-36 | Operational amplifiers (op-Amps): General considerations. One stage and two stage op-Amps. Gain boosting and common mode feedback. |
| 13 | 37-39 | Phase lock loops (PLL) : Basic PLL topology. Basic charge pump PLL. |
| 14 | 40-42 | Introduction to switch capacitor circuits. MOSFET as switches. Switch capacitor amplifiers. Switch capacitor integrators. |
Class participation will be judged by in-class evaluation; attendance will be recorded in every class.
Continuous assessment will be done in the form of quizzes, assignments, in-class evaluations.
Final Examination: A comprehensive term final examination will be held at the end of the Term following the guideline of academic Council.
Class Participation 10%
Continuous Assessment 20%
Final Examination 70%
Total 100%
Design of Analog CMOS Integrated Circuits. McGraw Hill International Edition 2001
CMOS Analog Circuit Design by Phillip E Allen and Douglas R Holberg, Oxford University Press, 2nd Edition
N.B. Besides going through relevant topics of the textbook, it is strongly advised that the students follow the class Lectures and discussions regularly for a thorough understanding of the topics.