Course Title: VLSI Circuits and Design
Type of Course: Optional, Theory
Offered to: EEE
Pre-requisite Course(s): None
Integrated circuit trends, choice of technology, Design approaches. MOS device : structure, operation, threshold voltage and characteristics equation for NMOS and PMOS devices. Principles of inverters : NMOS inverters design with resistive and NMOS enhancement transistor load. Ratioed and ratioless design.
The CMOS inverter : operation, transfer characteristics(TC). Propagation delay, rise time, fall time and power consumption estimation of CMOS inverter. Design for equal rise and fall time. Noise Margin. Variation of TC with respect to Wn and Wp. NMOS pass transistor, CMOS pass gate. Electro migration, and Latch-up in CMOS circuits.
Basic logic gates in CMOS. Synthesis of arbitrary combinational logic in CMOS, pseudo-NMOS, dynamic CMOS, clocked CMOS and CMOS domino logic.
Delay estimation, Elemore delay model, transistor sizing for minimum delay. Buffer chain design to drive large capacitive load. Logical efforts of path and the best number of stages.
Integrated circuit fabrication technology: photolithography, CMOS nanometer process flow.
Scaling of MOS transistor and secondary effects on device characteristics. Scaling of interconnect: RC delay modeling, repeaters and cascaded drives. Buffer chain design to drive large capacitive load. Logical efforts of paths and the best number of stages.
Integrated circuit fabrication technology: photolithography, Advanced CMOS nanometer process flow and enhancement of CMOS process, technology related CAD issues and manufacturing issues, design margin and PVT corners. Reliability issues: Latch-up, electro-migration.
High speed digital circuit design techniques, circuit families. Architecture for high speed design: Carry select, carry skip, carry look ahead and tree adders. Wallace tree multiplication.
Sequential circuit design: sequencing methods, maximum and minimum delay constrains, clock skew. Design of latches and flip-flops, clock Generation and synchronization, High-speed clock generation and distribution.
Memory elements design: SRAM and DRAM design. System timing consideration, static and dynamic CMOS memory array.
Finite State Machine design: Design of Moore Type and Mealy type FSM. Digital system design using Verilog. Functional verification of digital system using system Verilog, verification coverage, random test pattern generation and UVM.
Synthesis of Combinational and Sequential Logic (RTL). Postsynthesis Design Validation: timing verification by static timing analysis. Timing closure.
ASIC Cell based design, standard cell place and route design, timing directed placement design. Floor planning, power distribution and I/O cell placement.
The objective of this course is to master the design techniques of Very Large Scale Integrated Circuits emphasizing fundamentals as well as new paradigms that need to master in today’s industry. Hence the course covers basic as well as advanced aspects of the design of Very Large Scale Integrated (VLSI) circuit from design to verification and testing.
By the end of the course it is expected that the students will be able to design moderately complex digital VLSI chip, verify performance of the system and optimize the system for high speed and low power.
Fundamental understanding of concepts of Electronic Circuits I is required for this course.
| CO No. | CO Statement | Corresponding PO(s)* | Domains and Taxonomy level(s)** | Delivery Method(s) and Activity(-ies) | Assessment Tool(s) |
|---|---|---|---|---|---|
| CO1 | Apply the physics-based mathematical models of Semiconductor device to design digital circuit to do useful operation. | PO(a) | C2, C3 | Lectures, Discussions | Assignment, Class test, Final exam |
| CO2 | Synthesis Digital circuits based on specific operational requirements. | PO(b) | C4, C6 | Lectures, Discussions | Assignment, Class test, Final exam |
| CO3 | Design digital system based on specific requirements and design constraints such as power, speed, size etc. | PO(c), PO(d) | C4, C6 | Lectures, Discussions | Assignment, Final exam |
| CO4 | Apply circuit simulation tools to verify theoretical prediction of circuit performance using very complex but realistic device model. | PO(e) | C5, C6 | Lectures, Discussion | Assignment, Home work |
Cognitive Domain Taxonomy Levels: C1 – Knowledge, C2 – Comprehension, C3 – Application, C4 – Analysis, C5 – Synthesis, C6 – Evaluation, Affective Domain Taxonomy Levels: A1: Receive; A2: Respond; A3: Value (demonstrate); A4: Organize; A5: Characterize; Psychomotor Domain Taxonomy Levels: P1: Perception; P2: Set; P3: Guided Response; P4: Mechanism; P5: Complex Overt Response; P6: Adaptation; P7: Organization
Program Outcomes (PO): PO(a) Engineering Knowledge, PO(b) Problem Analysis, PO(c) Design/development Solution, PO(d) Investigation,
PO(e) Modern tool usage, PO(f) The Engineer and Society, PO(g) Environment and sustainability, PO(h) Ethics, PO(i) Individual work and team work,
PO(j). Communication, PO(k) Project management and finance, PO(l) Life-long Learning
* For details of program outcome (PO) statements, please see the departmental website or course curriculum
K 1 |
K 2 |
K 3 |
K 4 |
K 5 |
K 6 |
K 7 |
K 8 |
CP 1 |
CP 2 |
CP 3 |
CP 4 |
CP 5 |
CP 6 |
CP 7 |
CA 1 |
CA 2 |
CA 3 |
CA 4 |
CA 5 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| √ | √ | √ | √ | √ | √ | √ | √ | √ | √ | √ | √ |
| Week | Lectures | Topic |
|---|---|---|
| 1 | 1-3 | Finite State Machine design: Design of Moore Type and Mealy type FSM. Digital system design using Verilog |
| 2-3 | 4-9 | Functional verification of digital system using system Verilog: Flat and layered test benches, verification coverage, random test pattern generation and UVM. |
| 4 | 10-12 | Synthesis of Combinational and Sequential Logic (RTL). Postsynthesis Design Validation: timing verification by static timing analysis. Timing closure. |
| 5-6 | 13-18 | Integrated circuit trends, choice of technology, Design approaches. MOS device : structure, operation, threshold voltage and characteristics equation for NMOS and PMOS devices. Principles of inverters : NMOS inverters design with resistive and NMOS enhancement transistor load. Ratioed and ratioless design. The CMOS inverter : operation, transfer characteristics(TC). Propagation delay, rise time, fall time and power consumption estimation of CMOS inverter. Design for equal rise and fall time. Noise Margin. Variation of TC with respect to Wn and Wp. NMOS pass transistor, CMOS pass gate. Electro migration, and Latch-up in CMOS circuits. |
| 7 | 19-21 | Basic logic gates in CMOS. Synthesis of arbitrary combinational logic in CMOS, pseudo-NMOS, dynamic CMOS, clocked CMOS and CMOS domino logic. |
| 8 | 22-24 | Delay estimation, Elemore delay model, transistor sizing for minimum delay. Buffer chain design to drive large capacitive load. Logical efforts of path and the best number of stages. |
| 9 | 25-27 | Integrated circuit fabrication technology: photolithography, CMOS nanometer process flow. |
| 10-12 | 28-36 | High speed digital circuit design techniques : circuit families, architecture for high speed design, Carry select, carry skip, carry look ahead and tree adders. Wallace tree multiplication. Sequential circuit design: sequencing methods, maximum and minimum delay constrains, clock skew. Design of latches and flip-flops, clock Generation and synchronization, High-speed clock generation and distribution. |
| 13 | 37-39 | Memory elements design: SRAM and DRAM design. System timing consideration, static and dynamic CMOS memory array. |
| 14 | 40-42 | ASIC Cell based design, standard cell place and route design, timing directed placement design. Floor planning, power distribution and I/O cell placement. |
Class participation will be judged by in-class evaluation; attendance will be recorded in every class.
Continuous assessment will be done in the form of quizzes, assignments, in-class evaluations.
Final Examination: A comprehensive term final examination will be held at the end of the Term following the guideline of academic Council.
Class Participation 10%
Continuous Assessment 20%
Final Examination 70%
Total 100%
CMOS VLSI design: A Circuit and System Perspective by Neil H. E. Weste, David Harris & Ayan Banerjee, Pearson Education, 4th Edition.
CMOS VLSI design - A Circuits and Systems Perspective, 4th edition by Neil H. E. Weste and David Money Harris, Publisher : Addison Wesley.
Advanced Digtial Design with the Verilog HDL, Michael D. Ciletti, Prentice Hall of India Private Limited, 2005
System Verilog for Verification 3rd Edition Chris Spear and Greg Tumbush, Springer
Static Timing Analysis for Nanometer Designs – A practical Approach R. J Bhasker and Rakesh Chadha, Springer
Computer Organization and Design RISC-V Edition by David A. Patterson and John L. Hennessy, ELSEVIER
N.B. Besides going through relevant topics of the textbook, it is strongly advised that the students follow the class Lectures and discussions regularly for a thorough understanding of the topics.