Course Title: Digital Electronics
Type of Course: Compulsory, Theory
Offered to: EEE
Pre-requisite Course(s): None
Introduction to number systems and codes. Analysis and synthesis of digital logic circuits: Basic logic functions, Boolean algebra, combinational logic design, minimization of combinational logic. Introduction to Verilog Hardware Description Language programming and structural and behavioral design of digital systems using VerilogHDL, Verilog Timing analysis and test bench, MOSFET Digital circuits: NMOS inverter, CMOS inverter, CMOS logic circuits, Clocked CMOS logic circuits, transmission gates, sequential logic circuits, BJT digital circuits: ECL, TTL, STTL, BiCMOS, Memories: classification and architecture, RAM memory cells, Read only memory, data converters, Modular combinational circuit design: pass transistor, pass gates, multiplexer, demultiplexer and their implementation in CMOS, decoder, encoder, comparators, binary arithmetic elements and ALU design. Sequential circuits: latches, flip-flops timing analysis and power optimization of sequential circuits. Modular sequential logic circuit design: shift registers, counters and their applications. Asynchronous and synchronous sequential circuits. Dual Inline Packaged and Surface Mount Device (SMD) Integrated Circuits, Introduction to System Integration and Printed Circuit Board design, Design of a Simple-As-Possible (SAP) computer: SAP-1, selected concepts from SAP-2 (jump, call, return).
Introduce students concepts of number systems and digital electronics
Enable students to analyze and design combinational and sequential logic circuits
Give students a foundation on hardware description language based design (Verilog)
Fundamental understanding of concepts of Electronics I and Electronics II
| CO No. | CO Statement | Corresponding PO(s)* | Domains and Taxonomy level(s)** | Delivery Method(s) and Activity(-ies) | Assessment Tool(s) |
|---|---|---|---|---|---|
| CO1 | Analyze the structure and behaviour of different types of combinational and sequential digital logic circuits | PO(a) | C4 | Lectures, Homework | Class test, Final exam |
| CO2 | identify the requirements of physically implementing digital electronic circuits, different logic technologies and memory circuits using Verilog, FPGA and PCB design tools | PO(e) | C2 | Lectures, Homework | Class test, Final exam |
| CO3 | design combinational and sequential logic circuits with practical constraints using Verilog | PO(c) | C6 | Lectures, Tutorials, Homework | Assignment Class test, Final exam |
* Cognitive Domain Taxonomy Levels: C1 – Knowledge, C2 – Comprehension, C3 – Application, C4 – Analysis, C5 – Synthesis, C6 – Evaluation, Affective Domain Taxonomy Levels: A1: Receive; A2: Respond; A3: Value (demonstrate); A4: Organize; A5: Characterize; Psychomotor Domain Taxonomy Levels: P1: Perception; P2: Set; P3: Guided Response; P4: Mechanism; P5: Complex Overt Response; P6: Adaptation; P7: Organization
Program Outcomes (PO): PO(a) Engineering Knowledge, PO(b) Problem Analysis, PO(c) Design/development Solution, PO(d) Investigation,
PO(e) Modern tool usage, PO(f) The Engineer and Society, PO(g) Environment and sustainability, PO(h) Ethics, PO(i) Individual work and team work,
PO(j). Communication, PO(k) Project management and finance, PO(l) Life-long Learning
* For details of program outcome (PO) statements, please see the departmental website or course curriculum
| K1 | K2 | K3 | K4 | K5 | K6 | K7 | K8 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | A1 | A2 | A3 | A4 | A5 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 🗸 | 🗸 | 🗸 | 🗸 | 🗸 | 🗸 | 🗸 | 🗸 | 🗸 |
| Week | Topic | |
|---|---|---|
| 1 | Introduction to Number Systems and codes. Introduction to Boolean algebra, Introduction to VerilogHDL | Harris 1.4, 5.3, 1.5 |
| 2-3 | Analysis and synthesis of digital logic circuits: Basic logic function, combinational logic design, Universal logic gates, Minimization of combinational logic, k-map | Harris 2.1-2.9 |
| 4 | Programming and structural and behavioral design of digital systems using VerilogHDL, Verilog Timing analysis and test bench. Verilog synthesis with combinational logic | Harris 4 |
| 5 | ALU design (Adder, Subtractor, Comparator) | Harris 5.2- Floyd 6.1-6.3 |
| Winter Vacation | ||
| 6 | Decoder, encoder, Multiplexer, demultiplexer | Floyd 6.4-6.9 |
| 7 | MOSFET Digital circuits: NMOS inverter, CMOS inverter, CMOS logic circuits, Clocked CMOS logic circuits, transmission gates, Modular combinational circuit design: pass transistor, pass gates, and their implementation in CMOS | Harris 1.7-1.8 |
| 8 | Sequential circuits: different types of latches, flip-flops | Harris 3.1-3.2 Floyd 7.1-7.3 |
| 9 | Modular sequential logic circuit design: shift registers, counters, and application | Floyd 8.1-8.3, 9.2-9.7 |
| 10-11 | Asynchronous and synchronous sequential circuits., Introducing State Machine Design, State Minimization, Mille and Moore type state machine, design of simple FSM using Verilog | Harris 3.4 |
| 12-13 | Design of a Simple-As-Possible (SAP) computer: SAP-1, selected concepts from SAP-2 (jump, call, return) | Malvino Ch10,11 (partially) |
| 13 | Dual Inline Packaged and Surface Mount Device (SMD) Integrated Circuits, Introduction to System Integration and Printed Circuit Board design, Memories: classification and architecture, RAM memory cells, Read only memory | Lecture Slides Harris 5.5 |
Class Participation: Class participation and attendance will be recorded in every class.
Continuous Assessment: Continuous assessment any of the activities such as quizzes, assignment, presentation, etc. The scheme of the continuous assessment for the course will be declared on the first day of classes.
Final Examination: A comprehensive term final examination will be held at the end of the Term following the guideline of academic Council.
Class Participation 10%
Continuous Assessment 20%
Final Examination 70%
Total 100%
[Harris] Digital Design and Computer Architecture ARM Edition
[Floyd] Thomas L. Floyd, "Digital Fundamentals" 11th Edition, Pearson (2015)
[Malvino] Albert P. Malvino, Jerald A. Brown - Digital Computer Electronics-McGraw-Hill
(1993)
[Brown] Stephen Brown and Zvonko Vranesic, "Fundamentals of Digital Logic with Verilog Design" 3rd Edition, McGraw Hill (2014)
[Mano] Morris Mano and Michael Ciletti, "Digital Design with an Introduction to VerilogHDL" 5th Edition, Pearson (2013)