Course Title: Digital Electronics Laboratory
Type of Course: Compulsory, Sessional
Offered to: EEE
Pre-requisite Course(s): None
The sessional course will be conducted in two parts. In the first part of the sessional course, the students will perform experiments in relevance with the EEE 303. In the second part of the course, the students will perform design projects related to EEE 303 course contents to achieve specific program outcomes.
To perform experiments in relevance with the theoretical concepts of the course EEE 303: Digital Electronics
To conduct design projects in order to achieve specific program outcomes described in the Course Outline
Fundamental understanding of concepts of Electronics I and Electronics II
| CO No. | CO Statement | Corresponding PO(s)* | Domains and Taxonomy level(s)** | Delivery Method(s) and Activity(-ies) | Assessment Tool(s) |
|---|---|---|---|---|---|
| CO1 | Build digital electronic circuits using 74 series gates in breadboards | PO(a) | P3 | Labwork Labtest |
Lab Performance Lab Report Lab Test Quiz |
| CO2 | Construct Verilog programs and logic circuits for solving problems related to digital electronics, understanding the practical limitations | PO(e) | P5 | Labwork Labtest |
Lab Performance Lab Report Lab Test Quiz Project Report |
| CO3 | design a digital system to solve a relevant problem with due considerations to public health and safety, societal, cultural and environmental consideration | PO(c) | P7 | -- | Project Demonstration, Project Report |
| CO4 | demonstrate application of ethical principles and practices in the project, and evaluate peer team members ethically | PO(h) | A3 | -- | Peer evaluation, Report |
| CO5 | work effectively as an individual and as a team member towards the successful completion of the project | PO(i) | P4 | -- | Viva, Peer evaluation |
| CO6 | report effectively on the design done for CO3 with presentation, user-manual and detailed report | PO(j) | A3 | -- | Video Presentation Project Report |
Cognitive Domain Taxonomy Levels: C1 – Knowledge, C2 – Comprehension, C3 – Application, C4 – Analysis, C5 – Synthesis, C6 – Evaluation, Affective Domain Taxonomy Levels: A1: Receive; A2: Respond; A3: Value (demonstrate); A4: Organize; A5: Characterize; Psychomotor Domain Taxonomy Levels: P1: Perception; P2: Set; P3: Guided Response; P4: Mechanism; P5: Complex Overt Response; P6: Adaptation; P7: Organization
Program Outcomes (PO): PO(a) Engineering Knowledge, PO(b) Problem Analysis, PO(c) Design/development Solution, PO(d) Investigation,
PO(e) Modern tool usage, PO(f) The Engineer and Society, PO(g) Environment and sustainability, PO(h) Ethics, PO(i) Individual work and team work,
PO(j). Communication, PO(k) Project management and finance, PO(l) Life-long Learning
* For details of program outcome (PO) statements, please see the departmental website or course curriculum
| K1 | K2 | K3 | K4 | K5 | K6 | K7 | K8 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | A1 | A2 | A3 | A4 | A5 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 🗸 | 🗸 | 🗸 | 🗸 | 🗸 | 🗸 | 🗸 | 🗸 | 🗸 | 🗸 | 🗸 | 🗸 |
| Week | Delivery | Topic |
|---|---|---|
| 1 | Lecture | Introduction to overview of the experiments and projects, Lab Policies, Grading; formation of Teams for design project and lab works |
| 2 | Experiment 01 | Introduction To Basic Gates and Logic Simplification Techniques with discrete logic and Schematic Capture. |
| 3 | Experiment 02 | Design, Simulation, and Implementation of Arithmatic Circuits using 74 series ICs and VerilogHDL |
| 4 | Project Proposal Presentation |
Describe specific technical requirements to be attained during the project |
| 5 | Experiment 03 | Design, Simulation, and Implementation of Combinational Circuits Decoder/Encoder/Multiplexer Circuit using 74 series ICs and VerilogHDL |
| Experiment 04 | Design, Simulation and Test of Sequential Circuits Using Verilog And Implementation In FPGA. | |
| 6 | Project Design Presentation | Present/demonstrate the technical progress of the project Describe contextual knowledge to assess societal, health, safety, legal and cultural issues relevant to the project |
| 7 | Experiment 05 | Design, Simulation and Test of Finite State Machines Using Verilog And Implementation In FPGA. |
| 8 | Experiment 06 | Design, Simulation and Test of an SAP computer Machines Using Verilog And Implementation In FPGA. |
| 9 | Project Progress Presentation | Present/demonstrate the technical progress of the project Describe any necessary modification proposed to address public health and safety, cultural, societal, and environmental considerations related to the project |
| 10 | Lab Test | Lab Test performed on Experiment 1-6 |
| 11 | Project Progress Presentation | Present/demonstrate the technical progress of the project Evaluate the limitations of the technology used in the project Present the draft project report and draft presentation |
| 12 | Peer Assessment and Vivat | Present/demonstrate the technical progress, team and individual contribution and ethical principles applied to the design and implementation of the project Answer Technical Questions related to the project Individually and ethical principles applied to the design and implementation of the project Complete the Peer Assessment Survey to ethically evaluate the contribution to the project individually and as a team |
| 13 | Project Demonstration | Use multimedia and necessary documentation (user manual, video demonstration and project report) to clearly communicate the project Participate in the project showcase and communicate the design to industry stakeholders |
Lab Project
Students are to demonstrate the culmination of Course Outcomes through a small project, that can be implemented in roughly 4 Weeks. A Project Proposal needs to be prepared by the student group.
Project Requirements:
Must have conflicting / wide range solution (say improving speed of a circuit might also increase power consumption) (P(a))
Must be an open-ended problem with no obvious solution (P(b)) (Complex Engineering problem)
Project should address public health and safety, cultural, societal, and environmental considerations [CO3 (PO(c))]
Must be done with a CPLD, FPGA or 74 series ICs. Arduino or Microcontrollers are NOT allowed. Understand the limits of the used technology. [CO2(PO(e))]
Evaluation
10 Minutes recorded video presentation [with PPT slides] [CO6(P(j))]
Peer Evaluation of Group Members [CO4(PO(h))], [CO5(PO(i))]
Report in prescribed format with:
Technical Details of the Solution [CO6(PO(j))]
Teamwork and Individual Performance Report [CO5(PO(i))]
Technological Limit Evaluation [CO2(PO(e))]
public health and safety, cultural, societal, and environmental considerations [CO3(PO(c))]
ethics declaration statement [CO4(PO(h))]
Lab Reports and Lab Performance 10%
Lab test/Viva/Quiz 30%
*Final Project 50%
* Assessment will be performed by internal and external evaluators with industry experience
* marks distribution of the project will be declared at the beginning of the semester
No Textbooks are required. Lab Manual will be provided by instructors